The Agilent N4903A High-Performance Serial BERT (J-BERT) provides the only complete jitter tolerance test solution for characterization of serial gigabit devices.
The N4903A offers complete, integrated and calibrated jitter composition for stressed eye testing of receivers up to 12.5 Gb/s.
Automated and compliant jitter tolerance testing allows quick and accurate characterization for all popular serial bus standards, such as PCI Express, SATA, FB-DIMM, Fibre Channel, CEI, Gigabit Ethernet and XFP.
The N4903A matches to latest serial bus interfaces perfectly with its ability to analyze undeterministic traffic, generate complex pattern sequences, subrate clock outputs. Clockless and differential interfaces can be tested.
The N4903A is an expandable, future-proof BERT platform where all options can be configured to the current test needs and upgraded later when those needs change.
It is the ideal choice for R&D and validation teams who characterize and stress chips and transceiver modules with serial I/O ports up to 12.5 Gb/s.
- December, 2006: New improved CDR functionality. Installed J-BERTs can be upgraded
- Operating range 150 Mb/s to 7 Gb/s or to 12.5 Gb/s provides enough margin for today’s and tomorrows serial interfaces
- Cleanest eyes with transition times <20 ps and <9 ps pp jitter for accurate measurements
- Best match for serial interfaces: Built-in, tunable loop bandwidth CDR, differential I/Os, subrate clocks with any ratio 1:n
- Bit recovery mode (opt. A01) to analyze undeterministic traffic
- >0.5 UI jitter injection. Calibrated and integrated jitter injection (opt. J10, J20). All in one box: PJ, SJ, RJ, BUJ, ISI and sinusoidal interference for stressed eye test of a receiver
- External Delay Control Input for injection of any external jitter
- Automated jitter tolerance tests
- SSC clocking (opt. J11)
|
Read Descriptions of